A Multi-Kernel Multi-Code Polar Decoder Architecture.

Polar codes have received increasing attention in the past decade, and have been selected for the next generation of the wireless communication standard. Most research on polar codes has focused on codes constructed from a $2\times 2$ polarization matrix, called binary kernel: codes constructed from binary kernels have code lengths that are bound to powers of 2. A few recent works have proposed construction methods based on multiple kernels of different dimensions, not only binary ones, allowing code lengths different from powers of 2. In this paper, we design and implement the first multi-kernel successive cancellation polar code decoder in literature. It can decode any code constructed with binary and ternary kernels: the architecture, sized for a maximum code length $N_{\max }$ , is fully flexible in terms of code length, code rate, and kernel sequence. The decoder can achieve a frequency of over 1 GHz in 65 nm CMOS technology, and a throughput of 615 Mb/s. The area occupation ranges between 0.11 mm2 for $N_{\max }=256$ and 2.01 mm2 for $N_{\max }=4096$. Implementation results show an unprecedented degree of flexibility: with $N_{\max }=4096$ , up to 55 code lengths can be decoded with the same hardware, along with any kernel sequence and code rate. [ABSTRACT FROM AUTHOR]