Low power W-band divide-by-3 injection-locked frequency dividers with wide locking range in 90 nm CMOS.

In this work, we demonstrate two low-power and wide-locking-range W-band CMOS divide-by-3 injection-locked frequency dividers (ILFD3) using stacked cross-coupled-transistor topology. The first ILFD3 (ILFD3₁) uses an on-chip balun to transform the single input signal to differential output signals, which are amplified by the lower cross-coupled transistors and then inject the source terminals of the upper cross-coupled transistors. The second ILFD3 (ILFD3₂) uses a tail transistor to amplify the injection signal, which then injects the source terminals of the lower cross-coupled transistors. Due to the strong second harmonic signal (2f_inj) at the source terminals of the upper cross-coupled transistors, there are notable locked fundamental signals (f_inj) at the drain terminals of the upper cross-coupled transistors. ILFD3₁ occupies a chip area of 0.744 × 0.859 mm² (i.e. 0.639 mm²), consumes a low power of 1.6 mW, and achieves a locking range of 3.4 GHz (92.5-95.9 GHz). ILFD3₂ occupies a chip area of 0.87 × 0.775 mm² (i.e. 0.674 mm²), consumes a low power of 0.13 mW, and achieves an excellent locking range of 18 GHz (91.8-109.8 GHz), one of the best results ever reported for W-band CMOS ILFD3s. [ABSTRACT FROM AUTHOR]