Speed-Up Technique by Pre-Charging Load Capacitor in a SC Residue Circuit.

A novel passive charge re-distribution technique for switched capacitor residue circuits used in pipeline analog to digital converters is presented. It is based on pre-charging the load capacitor to the proper voltage during the previous phase, connecting the pre-charged load capacitor to the output of the operational trans-conductance amplifiers (OTA) during the evaluation phase, and hence pulling the charge so that the initial voltage step in the OTA input is instantaneously minimized. The OTA therefore skips the slew region and enters into the linear settling region, leaving just a minor charge to be moved by the OTA. A double-sampling, OTA-sharing SC residue with 1.5-bit MDAC is designed using 90-nm generic CMOS PDK with 1.2-V supply voltage. Simulation results of a 10-bit, 100 MS/s SC residue with the proposed technique show that the conversion rate can be increased over 30% compared to the conventional SC residue circuit. [ABSTRACT FROM AUTHOR]