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Challenges to Partial Switching of Hf0.8Zr0.2O2 Gated Ferroelectric FET for Multilevel/Analog or Low-Voltage Memory Operation.

Authors :
Chatterjee, Korok
Kim, Sangwan
Karbasian, Golnaz
Kwon, Daewoong
Tan, Ava J.
Yadav, Ajay K.
Serrao, Claudy R.
Hu, Chenming
Salahuddin, Sayeef
Source :
IEEE Electron Device Letters; Sep2019, Vol. 40 Issue 9, p1423-1426, 4p
Publication Year :
2019

Abstract

The ability to partially switch an FeFET could enable their use as an embedded low-voltage memory and as analog weight storage in artificial neural networks (ANNs). We report on memory characterization of FeFETs gated with 5.5-nm Hf0.8Zr0.2O2, fabricated on fully depleted silicon-on-insulator using a self-aligned, gate last process. We find that for a single device, excellent elevated temperature retention, program/erase endurance, and read endurance are obtained; however, there is significant device to device variability in the response of the ferroelectric to a partially switching program pulse, which may require the use of feedback in programming. [ABSTRACT FROM AUTHOR]

Details

Language :
English
ISSN :
07413106
Volume :
40
Issue :
9
Database :
Complementary Index
Journal :
IEEE Electron Device Letters
Publication Type :
Academic Journal
Accession number :
138275959
Full Text :
https://doi.org/10.1109/LED.2019.2931430