FPGA BASED IMPLEMENTATION OF MEDIAN FILTER USING COMPARE AND EXCHANGE UNIT.

Over the past few years, so many new solutions are gaining popularity in the software industry. All these solutions require a fast and parallel data manipulation. An attempt has been made to design median filter with high throughput and good latency to suppress the impulse based noise on real time signal and image processing applications. It is partially affected by the median filter and its bias of the input stream is directly above the average of mathematical analysis. An efficient VLSI suitable hardware implementation of a median filter is presented, that uses compare and exchange unit. The proposed hardware structure reduces the hardware requirements and has a faster processing speed, when compared with some other existing techniques. The input numbers or streams are used to construct an algorithm. By using this algorithm, the median number can be found out. The proposed technique can be implemented with perfect shuffle interconnects between active stages of compare and exchange elements. In this paper, all the designs are synthesized and created using MAX PLUS- II from ALTERA with f = 486.38 MHz. [ABSTRACT FROM AUTHOR]