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Tag Compression for Low Power in Dynamically Customizable Embedded Processors.

Source :
IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems; Jul2004, Vol. 23 Issue 7, p1031-1047, 17p
Publication Year :
2004

Abstract

We present a methodology for power reduction by instruction/data cache-tag compression for low-power embedded processors. By statically analyzing the code/data memory layouts for the application hot spots, a variety of proposed schemes for effective tag-size reduction can be employed for power minimization in instruction and data caches. The schemes rely on significantly reducing the number of tag bits stored in the tag arrays for cache-conflict identification, thus considerably decreasing the number of active bitlines, sense amps, and comparator cells. We present a set of tag compression techniques and evaluate each of them separately in terms of efficiency and required hardware sup- port. A detailed very large scale integrated implementation has been performed and a number of experimental results on a set of embedded applications is reported for each technique. Energy dissipation decreases of up to 95% can be observed for the tag arrays, implying significant energy reductions in the range of 50% when amortized across the overall cache subsystem. [ABSTRACT FROM AUTHOR]

Details

Language :
English
ISSN :
02780070
Volume :
23
Issue :
7
Database :
Complementary Index
Journal :
IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems
Publication Type :
Academic Journal
Accession number :
13885048
Full Text :
https://doi.org/10.1109/TCAD.2004.829823