An energy-efficient, 6 GS/s dynamic comparator in 90 nm CMOS technology.

In this paper, a two-stage dynamic comparator circuit is proposed, which considerably reduces the power consumption as well as the power-delay product parameter, while improves the speed. Furthermore, the performance of the pre-amplifier stage in the proposed design is improved which properly reduces the kick-back noise as well as the power consumption. The proposed circuit operates at 1 V supply at the clock frequency of 6 GHz (high-speed scenario), which results in the static and dynamic power consumption of 112.77 nW and 848 μW, respectively. Moreover, the delay of the circuit is 36.6 ps, while the output offset voltage is only 8 mV, with the kick-back noise of 48 mV. On the other hand, the circuit can operate at 1 V supply and frequency of 500 MHz (low-power scenario), which results in the reduced static and dynamic power consumption of 112.77 nW and 188.9 μW, respectively while the offset of the circuit can be reduced to only 1 mv at the delay of 46.4 ps and kick-back noise of 39.75 mV. [ABSTRACT FROM AUTHOR]