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A Study of High-Temperature Effects on an Asymmetrically Doped Vertical Pillar-Type Field-Effect Transistor.
- Source :
- IEEE Transactions on Nanotechnology; 2020, Vol. 19, p52-55, 4p
- Publication Year :
- 2020
-
Abstract
- The effects of high temperature on an asymmetrically doped vertical pillar-type metal-oxide-semiconductor field-effect transistor (MOSFET) were investigated. An asymmetrically doped source and drain (S/D) can be easily formed in a vertical pillar-type FET due to the unique pillar structure. When high temperature is applied to the asymmetric S/D of a vertical pillar-typed silicon nanowire, it affects mobility and carrier injection differently. It decreases mobility by phonon scattering for heavily doped S and intermediately doped D. In contrast, it enhances carrier injection for intermediately doped S and heavily doped D. Thus the ON-state current (ION) shows opposite dependencies at high temperature. This tendency was verified by electrical measurements and supporting simulations. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 1536125X
- Volume :
- 19
- Database :
- Complementary Index
- Journal :
- IEEE Transactions on Nanotechnology
- Publication Type :
- Academic Journal
- Accession number :
- 140826061
- Full Text :
- https://doi.org/10.1109/TNANO.2019.2958099