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A Novel Heuristic Search Method for Two-Level Approximate Logic Synthesis.
- Source :
- IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems; Mar2020, Vol. 39 Issue 3, p654-669, 16p
- Publication Year :
- 2020
-
Abstract
- Recently, much attention has been paid to approximate computing, a novel design paradigm for error-tolerant applications. It can significantly reduce area, power, and delay of circuits by introducing an acceptable amount of error. In this paper, we propose a new heuristic method for two-level approximate logic synthesis. The problem is to identify an approximate sum-of-product (SOP) expression under a given error rate (ER) constraint so that it has the fewest literals. The basic idea of our method is to find an optimal set of input combinations for 0-to-1 output complement (SICC). For this purpose, we first identify all prime SICCs, which are fundamental SICCs in the sense that the optimal SICC is very likely to be a union of a subset of the prime SICCs. Then, we search among all subsets of the prime SICCs the optimal subset, which leads to a final good approximate SOP. We further propose four speed-up techniques. The experiments on benchmarks showed that our method is better than the previous state-of-the-art method and our speed-up techniques are effective. For an ER threshold of 0.8%, our method can reduce 15.8% literals on average. [ABSTRACT FROM AUTHOR]
- Subjects :
- LOGIC design
HEURISTIC
DELAY lines
BOOLEAN functions
ERROR analysis in mathematics
Subjects
Details
- Language :
- English
- ISSN :
- 02780070
- Volume :
- 39
- Issue :
- 3
- Database :
- Complementary Index
- Journal :
- IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems
- Publication Type :
- Academic Journal
- Accession number :
- 143313098
- Full Text :
- https://doi.org/10.1109/TCAD.2018.2890532