Back to Search
Start Over
Selective Flip-Flop Optimization for Reliable Digital Circuit Design.
- Source :
- IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems; Jul2020, Vol. 39 Issue 2, p1484-1497, 14p
- Publication Year :
- 2020
-
Abstract
- Runtime variability sources, such as bias temperature instability (BTI) and supply voltage fluctuation affect both timing and functionality of the flip-flops inside a VLSI circuit. In this paper, we propose a method to improve the timing and reliability of the VLSI circuits by optimizing the flip-flops for resiliency against aging and supply voltage fluctuation. In the proposed selective reliability optimization method, we first extend the standard cell libraries by adding optimized versions of the flip-flops designed for better resiliency against severe BTI impact and/or supply voltage fluctuation. Then, we optimize the VLSI circuit by replacing the aging-critical and voltage-drop-critical flip-flops (VC) of the circuit with the reliability-optimized versions to improve the timing and the reliability of the entire circuit in a cost-effective way. The simulation results show that incorporating the optimized flip-flops in a processor can prolong the lifetime of the processor by 36.9% compared to the original design, which translates into better reliability. This is achieved with negligible leakage overhead (less than 0.1% on the processor) and no area overhead which facilitates the integration of the proposed method in the standard VLSI design flow. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 02780070
- Volume :
- 39
- Issue :
- 2
- Database :
- Complementary Index
- Journal :
- IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems
- Publication Type :
- Academic Journal
- Accession number :
- 143857965
- Full Text :
- https://doi.org/10.1109/TCAD.2019.2917848