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A High Resolution DPWM Based on Synchronous Phase-Shifted Circuit and Delay Line.
- Source :
- IEEE Transactions on Circuits & Systems. Part I: Regular Papers; Aug2020, Vol. 67 Issue 8, p2685-2692, 8p
- Publication Year :
- 2020
-
Abstract
- In this paper, a hybrid architecture of digital pulse width modulator (DPWM) with high resolution is proposed. Furthermore, to enhance linearity performance, the critical path is optimized by a novel synchronous phase-shifted circuit. A carry chain-based delay line is also utilized to improve time resolution. A 14-bit DPWM with the proposed architecture is implemented and tested by Altera Cyclone IV FPGA. The experiment results show that the DPWM achieves high linearity, where $R^{2}$ maintains over 0.9994. Besides, the output duty cycle covers a wide range from 0.9429% to 99.2% and the time resolution is about 41.3ps. [ABSTRACT FROM AUTHOR]
- Subjects :
- DELAY lines
PHASE-locked loops
PULSE width modulation
Subjects
Details
- Language :
- English
- ISSN :
- 15498328
- Volume :
- 67
- Issue :
- 8
- Database :
- Complementary Index
- Journal :
- IEEE Transactions on Circuits & Systems. Part I: Regular Papers
- Publication Type :
- Periodical
- Accession number :
- 144890701
- Full Text :
- https://doi.org/10.1109/TCSI.2020.2977146