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FPGA implementation of an arbitrary resample rate, FOH, pulse width modulator.
- Source :
- Journal of Engineering; Sep2019, Vol. 2019 Issue 9, p3730-3735, 6p
- Publication Year :
- 2019
-
Abstract
- This study presents a field-programmable gate array implementation of an advanced pulse-width modulator which combines a first-order hold (FOH) with phase accumulator carrier pulse-width modulation (PACPWM) for significantly reduced phase delay, and bandwidth extension in multi-level applications. The FOH block supports arbitrary resampling rates and operates in a single clock cycle for simple integration into multi-rate or asynchronous systems. The proposed modulator is validated experimentally, with performance matching that predicted for both FOH and a zero-order hold (ZOH). For PWM with 8 kHz carrier frequency and 50.4 kHz resampling frequency, a 15 degree phase delay advantage is demonstrated for FOH compared with ZOH across the 5–10 kHz modulation band. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 20513305
- Volume :
- 2019
- Issue :
- 9
- Database :
- Complementary Index
- Journal :
- Journal of Engineering
- Publication Type :
- Academic Journal
- Accession number :
- 148148605
- Full Text :
- https://doi.org/10.1049/joe.2018.8021