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Design optimization of sub-5 nm node nanosheet field effect transistors to minimize self-heating effects.
- Source :
- Journal of Vacuum Science & Technology: Part B-Nanotechnology & Microelectronics; Jan2021, Vol. 39 Issue 1, p1-11, 11p
- Publication Year :
- 2021
-
Abstract
- In this work, self-heating effects (SHE) in nanometer-scale metal-oxide-semiconductor field-effect transistor structures—namely, FinFETs (FFs), nanosheet gate-all-around FETs (NSFs), and nanowire gate-all-around FETs (GAAFs)—are investigated via three-dimensional device electrothermal simulations using technology computer-aided design software tools. Initially, transistor design parameter values are set so that their on-state currents are similar for the same operating voltage (V<subscript>DD</subscript>). It is found that NSFs and GAAFs are more susceptible to SHE and that p-channel transistors have higher peak internal temperatures than do their n-channel counterparts due to the poor thermal conductivity of the silicon-germanium used as the p-type source/drain material. Subsequently, the on-state currents of FFs, NSFs, and GAAFs are compared under the constraint of identical peak internal temperature, which is required to ensure long-term reliability, revealing that NSFs and GAAFs offer no performance advantage over FFs under this constraint. Design optimization of p-channel NSFs for minimal SHE is subsequently investigated. It is found that with such optimization, NSFs operating at lower V<subscript>DD</subscript> (for similar SHE) can achieve similar on-state current as FFs. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 21662746
- Volume :
- 39
- Issue :
- 1
- Database :
- Complementary Index
- Journal :
- Journal of Vacuum Science & Technology: Part B-Nanotechnology & Microelectronics
- Publication Type :
- Academic Journal
- Accession number :
- 148312409
- Full Text :
- https://doi.org/10.1116/6.0000675