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Analysis of Edge Effect Occurring in Non-Volatile Ferroelectric Transistors.
- Source :
- IEEE Electron Device Letters; Mar2021, Vol. 42 Issue 3, p315-318, 4p
- Publication Year :
- 2021
-
Abstract
- This study focuses on the interaction between the oxide layer area of a transistor and its ferroelectric layer area. An experimental comparison of transistor oxide layer area demonstrates that the larger the ratio of oxide to ferroelectric layers, the larger the on/off ratio, thus improving performance. A subsequent experiment aimed to further demonstrate this in different sized devices, and changing the ratio of $\text{A}_{\text {HZO}}/\text{A}_{\text {SiO2}}$ (the area of HfZrOx divided by oxide layer) showed the same tendency as above, but also produced an unexpected finding in that a comparison of on/off ratio exhibits an abnormal electric characteristic. This study discusses this abnormal electric characteristic and proposes an explanatory physical model. [ABSTRACT FROM AUTHOR]
- Subjects :
- TRANSISTORS
EDGES (Geometry)
NONVOLATILE memory
LOGIC circuits
Subjects
Details
- Language :
- English
- ISSN :
- 07413106
- Volume :
- 42
- Issue :
- 3
- Database :
- Complementary Index
- Journal :
- IEEE Electron Device Letters
- Publication Type :
- Academic Journal
- Accession number :
- 148969897
- Full Text :
- https://doi.org/10.1109/LED.2021.3054418