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A Binary Translation Framework for Automated Hardware Generation.

Authors :
Paulino, Nuno
Bispo, Joao
Ferreira, Joao C.
Cardoso, Joao M. P.
Source :
IEEE Micro; Jul-Aug2021, Vol. 41 Issue 4, p15-23, 9p
Publication Year :
2021

Abstract

As applications move to the edge, efficiency in computing power and power/energy consumption is required. Heterogeneous computing promises to meet these requirements through application-specific hardware accelerators. Runtime adaptivity might be of paramount importance to realize the potential of hardware specialization, but further study is required on workload retargeting and offloading to reconfigurable hardware. This article presents our framework for the exploration of both offloading and hardware generation techniques. The framework is currently able to process instruction sequences from MicroBlaze, ARMv8, and riscv32imaf binaries, and to represent them as Control and Dataflow Graphs for transformation to implementations of hardware modules. We illustrate the framework's capabilities for identifying binary sequences for hardware translation with a set of 13 benchmarks. [ABSTRACT FROM AUTHOR]

Details

Language :
English
ISSN :
02721732
Volume :
41
Issue :
4
Database :
Complementary Index
Journal :
IEEE Micro
Publication Type :
Academic Journal
Accession number :
151283047
Full Text :
https://doi.org/10.1109/MM.2021.3088670