A full input range, 1–1.8 V voltage supply scalable analog voltage comparator in 180nm CMOS.

A voltage supply scalable analog voltage comparator for a wide input range is presented in this paper. A digital gate-based methodology is used to design the comparator in order to extend the use of automation in the analog designs. Therefore, the proposed comparator is enormously cost-effective, reduces the time-to-market, scalable to newer technologies, and more immune to process variations than the conventional CMOS analog voltage comparators. The comparator is designed using Semi-Conductor Laboratory (SCL) 180 nm digital CMOS technology at a supply voltage of 1.8 V. The power consumption of the proposed comparator is 160 µW approximately with total delay and offset voltage of 1.63 ns and 4.28 mV, respectively. Also, 4-bit and 5-bit flash ADC is designed as an application. The measured values of DNL/INL are ± 0.4/± 0.4 LSB and 0.42/± 0.6 LSB for 4-bit and 5-bit, respectively. [ABSTRACT FROM AUTHOR]