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CMP Process Optimization Engineering by Machine Learning.

Authors :
Yu, Hsiang-Meng
Lin, Chih-Chen
Hsu, Min-Hsuan
Chen, Yen-Ting
Chen, Kuang-Wei
Luoh, Tuung
Yang, Ling-Wuu
Yang, Tahone
Chen, Kuang-Chao
Source :
IEEE Transactions on Semiconductor Manufacturing; Aug2021, Vol. 34 Issue 3, p280-285, 6p
Publication Year :
2021

Abstract

Advanced Chemical-mechanical polishing (CMP) process not only needs to maintain stable run-to-run thickness control but also achieve better within wafer/within chip planarization performance. Furthermore, slurries or other consumable parts, like PAD and Disks selection are also the keys for CMP process optimization. The most difficult thing in CMP process is to have capability to predict and cover the various topologies and layout densities patterned wafers and preventing the hot spots occurrences. In this study, different Neural-Network algorithm with data pre-processing models are implemented to the in-line CMP CLC tuning and dishing/erosion prediction at various topology/pattern density test vehicle pattern wafers. Transfer learning technique is implemented on the original Neural -Network algorithm model, the behavior of real product can be simulated and predicted based on the knowledge of test vehicle database successfully. With the aid of multiple layer erosion/ dishing Neural-Network algorithm model prediction, the potential high risky hot spots can be highlighted at the initial layout design stage, then further shorten the turn-around time of design layout validation. [ABSTRACT FROM AUTHOR]

Details

Language :
English
ISSN :
08946507
Volume :
34
Issue :
3
Database :
Complementary Index
Journal :
IEEE Transactions on Semiconductor Manufacturing
Publication Type :
Academic Journal
Accession number :
153127989
Full Text :
https://doi.org/10.1109/TSM.2021.3072361