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Majority Logic Circuit Minimization Using Node Addition and Removal.

Authors :
Ko, Chang-Cheng
Lin, Chia-Chun
Chen, Yung-Chih
Wang, Chun-Yao
Source :
IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems; Mar2022, Vol. 41 Issue 3, p642-655, 14p
Publication Year :
2022

Abstract

Quantum-dot cellular automata (QCA) is considered as a promising emerging technology due to its low power dissipation and high device density. Since the majority function is the main operation in QCA circuits, minimizing the number of majority gates in QCA circuits is crucial to the corresponding QCA circuit minimization. A previous work used the node-merging technique to replace one target node with an existing substitute node in majority circuits for optimization. However, this technique may fail when no substitute nodes exist for a target node. In this article, we propose an enhanced optimization technique for majority circuits by adding a new node into the circuits and removing the target node and its fanin nodes. The experimental results show that this technique improves the results of the node-merging technique on a set of EPFL logic synthesis benchmarks. Additionally, this enhanced technique can work together with other optimization techniques. The circuit size reduction in the integrated approach reaches 1.26 times as compared to the results using the node-merging technique. [ABSTRACT FROM AUTHOR]

Details

Language :
English
ISSN :
02780070
Volume :
41
Issue :
3
Database :
Complementary Index
Journal :
IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems
Publication Type :
Academic Journal
Accession number :
155458658
Full Text :
https://doi.org/10.1109/TCAD.2021.3060648