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Approximate Multipliers Using Static Segmentation: Error Analysis and Improvements.
- Source :
- IEEE Transactions on Circuits & Systems. Part I: Regular Papers; Jun2022, Vol. 69 Issue 6, p2449-2462, 14p
- Publication Year :
- 2022
-
Abstract
- Approximate multipliers are used in error-tolerant applications, sacrificing the accuracy of results to minimize power or delay. In this paper we investigate approximate multipliers using static segmentation. In these circuits a set of $m$ contiguous bits (a segment of $m$ bits) is extracted from each of the two $n$ -bits operand, the two segments are in input to a small $m\times m$ internal multiplier whose output is suitably shifted to obtain the result. We investigate both signed and unsigned multipliers, and for the latter we propose a new segmentation approach. We also present simple and effective correction techniques that can significantly reduce the approximation error with reduced hardware costs. We perform a detailed comparison with previously proposed approximate multipliers, considering a hardware implementation in 28 nm technology. The comparison shows that static segmented multipliers with the proposed correction technique have the desirable characteristic of being on (or close to) the Pareto-optimal frontier for both power vs normalized mean error distance and power vs mean relative error distance trade-off plots. These multipliers, therefore, are promising candidates for applications where their error performance is acceptable. This is confirmed by the results obtained for image processing and image classification applications. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 15498328
- Volume :
- 69
- Issue :
- 6
- Database :
- Complementary Index
- Journal :
- IEEE Transactions on Circuits & Systems. Part I: Regular Papers
- Publication Type :
- Periodical
- Accession number :
- 157191471
- Full Text :
- https://doi.org/10.1109/TCSI.2022.3152921