Joint Application Mapping/Interconnect Synthesis Techniques for Embedded Chip-Scale Multiprocessors.

MLA

Bambha, Neal K., and Shuvra S. Bhattacharyya. “Joint Application Mapping/Interconnect Synthesis Techniques for Embedded Chip-Scale Multiprocessors.” IEEE Transactions on Parallel & Distributed Systems, vol. 16, no. 2, Feb. 2005, pp. 99–112. EBSCOhost, https://doi.org/10.1109/TPDS.2005.20.

APA

Bambha, N. K., & Bhattacharyya, S. S. (2005). Joint Application Mapping/Interconnect Synthesis Techniques for Embedded Chip-Scale Multiprocessors. IEEE Transactions on Parallel & Distributed Systems, 16(2), 99–112. https://doi.org/10.1109/TPDS.2005.20

Chicago

Bambha, Neal K., and Shuvra S. Bhattacharyya. 2005. “Joint Application Mapping/Interconnect Synthesis Techniques for Embedded Chip-Scale Multiprocessors.” IEEE Transactions on Parallel & Distributed Systems 16 (2): 99–112. doi:10.1109/TPDS.2005.20.