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Gate Oxide Degradation Condition Monitoring Technique for High-Frequency Applications of Silicon Carbide Power MOSFETs.
- Source :
- IEEE Aerospace & Electronic Systems; Jan2023, Vol. 38 Issue 1, p1079-1091, 13p
- Publication Year :
- 2023
-
Abstract
- Gate oxide degradation, which considerably affects turn-on/-off dynamics of the switch, embraces a large percentage of chip-related failure modes both in silicon and silicon carbide power MOSFETs. The gate oxide layer is thinner in silicon carbide power MOSFETs in comparison to their silicon-based counterparts. Consequently, the problem of gate oxide degradation has become a more crucial impediment in achieving reliable performance in silicon carbide power MOSFETs. This problem is even more severe in high-frequency applications due to higher EMI signature and complicated and costly measurement. In this article, a reliable fully analog cost-effective gate oxide degradation condition monitoring technique is proposed and validated. High-order harmonics magnitudes of drain–source voltage are used to produce a dc signal as the aging precursor of the gate oxide region. Using a dedicated degradation setup, the credibility of the developed condition monitoring technique was examined at different rates of gate oxide degradation for 650-V/22-A silicon carbide discrete MOSFET. In 200-kHz, 217-V switch operation, the proposed precursor showed 68% change in comparison to its initial value. This brings a high-resolution assessment on the reliability level of the switch gate oxide region. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 08858985
- Volume :
- 38
- Issue :
- 1
- Database :
- Complementary Index
- Journal :
- IEEE Aerospace & Electronic Systems
- Publication Type :
- Academic Journal
- Accession number :
- 160685973
- Full Text :
- https://doi.org/10.1109/TPEL.2022.3198291