Small-Area SAR ADCs With a Compact Unit-Length DAC Layout.

This brief presents four small-area SAR ADCs with a resolution from 8 to 11 bits. Two area-saving techniques are utilized. First, the DAC layout is implemented with custom designed unit-length capacitors, which are optimized for each resolution to minimize the chip area. Second, dynamic logic is applied to the 8-bit design to further reduce the number of transistors and save area. Fabricated in 65 nm CMOS, the 8/9/10/11-bit SAR ADCs only occupy $20\times 21\,\,\mu \text{m}$ , $20\times 36\,\,\mu \text{m}$ , $36\times 36\,\,\mu \text{m}$ and $36\times 36\,\,\mu \text{m}$ , respectively. At 10 MHz sampling rate, their measured ENOB is 7.5, 8.3, 9.1 and 9.8 bits with an SFDR of 65.4 dB, 67.4 dB, 78.0 dB and 76.5 dB, respectively. Compared to prior-art, these designs achieve the smallest areas for the achieved ENOBs. [ABSTRACT FROM AUTHOR]