A 35-GHz Bandwidth 30 GSa/s InP Track-and-Hold Amplifier Using Enhanced f T -Doubler Technique.

In this brief, a high-speed wideband track-and-hold amplifier (THA) is implemented in a $0.8~{\mu }\text{m}$ InP double-heterojunction bipolar transistor (DHBT) process. This THA is based on a base-collector (b-c) switching diode architecture and achieves a −3 dB bandwidth of 35 GHz at a sampling rate of 30 GSa/s. For the first time, an enhanced unity-gain frequency (${f_{T}}$) doubler and an active peaking technique are used together in the design of the b-c switching diode sampler. The dominant pole of the THA is canceled by one zero produced by the active peaking structure. This is one step to improve the bandwidth. Secondly, the enhanced ${f_{T}}$ -doubler structure improves the driving capability of the input buffer at high frequencies. Therefore, the bandwidth of the THA is further extended. The measurement results show a total harmonic distortion (THD) of <−30.0 dBc and a maximum spurious-free dynamic range (SFDR) of 47.07 dB at a 30-GSa/s sampling rate. S-parameter tests show a better than −43 dB isolation within 45 GHz in hold-mode, and a −3 dB bandwidth of 35 GHz in track-mode under a 165 GHz device ${f_{T}}$. The proposed THA has the potential for high-speed broadband applications due to its competitive performance. [ABSTRACT FROM AUTHOR]