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Zero-voltage and frequency pattern selection for DC-link loss minimization in PWM-VSI drives.
- Source :
- Electrical Engineering; Feb2023, Vol. 105 Issue 1, p349-358, 10p
- Publication Year :
- 2023
-
Abstract
- The modulation of a voltage source inverter output causes losses and harmonic distortions on the load side and the DC-link capacitor due to the discrete switching of the semiconductors. High-frequent voltage pulses are digitally programmed to control the inverter output and determine the harmonic distortions. This paper presents an optimization in terms of pulse- and frequency-pattern selection for reducing load distortions while keeping DC-link losses minimal. In detail, the fact that pulse and frequency patterns are independent from each other is utilized and a modified three-zone hybrid space vector pulse-width modulation is proposed where optimal frequency patterns are selected for every carrier cycle. Simulations and experimental results validate the optimizations. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 09487921
- Volume :
- 105
- Issue :
- 1
- Database :
- Complementary Index
- Journal :
- Electrical Engineering
- Publication Type :
- Academic Journal
- Accession number :
- 162033261
- Full Text :
- https://doi.org/10.1007/s00202-022-01627-z