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Pyramid P+ area in SOI junction-less MOSFET for logic applications: DC investigation.
- Source :
- Applied Nanoscience; Aug2023, Vol. 13 Issue 8, p5711-5717, 7p
- Publication Year :
- 2023
-
Abstract
- This work presents silicon-on-insulator (SOI) junction-less FETs (C-JLFET) with a pyramid P<superscript>+</superscript> area within the buried oxide region (PP-JLFET). The Silvaco software analysis shows that the PP-JLFET with P<superscript>+</superscript> area within the BOX layer has improved the I<subscript>ON</subscript>/I<subscript>OFF</subscript> ratio of ~ 10<superscript>10</superscript> and causes the proposed device to be suitable for logic operations. The principal concept of this paper concentrates on enhancing the depletion region for obtaining a smaller off-current (I<subscript>OFF</subscript>) ~ 10<superscript>–15</superscript>. Although the on-current (I<subscript>ON</subscript>) reduced slightly, but this decrement is very small value. Also, another purpose is to achieve a better self-heating effect (SHE), which is obtained by embedding a silicon pyramid P<superscript>+</superscript> area with a larger thermal conductivity than the buried oxide region. SHE improves from 308 to 325 K in the proposed device versus the conventional JLFET. Effects including carrier density, lattice temperature, SHE, and kink effect have been investigated, and the PP-JLFET results demonstrate that the proposed device improves the device characteristics versus C-JLFET. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 21905509
- Volume :
- 13
- Issue :
- 8
- Database :
- Complementary Index
- Journal :
- Applied Nanoscience
- Publication Type :
- Academic Journal
- Accession number :
- 164579596
- Full Text :
- https://doi.org/10.1007/s13204-023-02808-3