Pyramid P+ area in SOI junction-less MOSFET for logic applications: DC investigation.

This work presents silicon-on-insulator (SOI) junction-less FETs (C-JLFET) with a pyramid P⁺ area within the buried oxide region (PP-JLFET). The Silvaco software analysis shows that the PP-JLFET with P⁺ area within the BOX layer has improved the I_ON/I_OFF ratio of ~ 10¹⁰ and causes the proposed device to be suitable for logic operations. The principal concept of this paper concentrates on enhancing the depletion region for obtaining a smaller off-current (I_OFF) ~ 10^–15. Although the on-current (I_ON) reduced slightly, but this decrement is very small value. Also, another purpose is to achieve a better self-heating effect (SHE), which is obtained by embedding a silicon pyramid P⁺ area with a larger thermal conductivity than the buried oxide region. SHE improves from 308 to 325 K in the proposed device versus the conventional JLFET. Effects including carrier density, lattice temperature, SHE, and kink effect have been investigated, and the PP-JLFET results demonstrate that the proposed device improves the device characteristics versus C-JLFET. [ABSTRACT FROM AUTHOR]