FinFET-based 11T sub-threshold SRAM with improved stability and power.

This paper presents a single-ended 11T sub-threshold SRAM (SE11T) based on 10-nm FinFET technology. The performance of the proposed design is evaluated and compared with those of other state-of-the-art SRAMs namely 6T, 8T, DIRP10T, ST2, PPN10T, and FC11T at V_DD = 0.3 V. The proposed design improves read stability by 2.08X/1.31X/1.03X compared to 6T/ST2/PPN10T due to the read-decoupling technique. Furthermore, it improves writability by 1.42X/2.85X/1.35X/1.28X compared to 6T/DIRP10T/ST2/PPN10T owing to feedback-cutting scheme. The use of write bitline free structure make the proposed SRAM consumes at least 2.79X lower dynamic power. The static power is reduced in the proposed SRAM by at least 1.09X. The reduction is because of the stacking of the transistors, the long path from power V_DD to ground, and eliminated leakage in read path. The proposed SRAM works reliably even when exposed to extreme process variations. The proposed bitcell occupies a 1.46X/1.19X higher area than that of 6T/8T. The proposed design improves most of the design metrics and can be an efficient candidate for portable applications with budgeted power. [ABSTRACT FROM AUTHOR]