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FPGA architecture for convolutional neural network training.

Authors :
Chen, Jianlang
Qiu, Danfeng
Xie, Yudong
Huo, Liangzhou
Chen, Xin
Source :
Proceedings of SPIE; 2/6/2024, Vol. 12799, p127993W-127993W-6, 1p
Publication Year :
2024

Details

Language :
English
ISSN :
0277786X
Volume :
12799
Database :
Complementary Index
Journal :
Proceedings of SPIE
Publication Type :
Conference
Accession number :
172919105
Full Text :
https://doi.org/10.1117/12.3006102