Back to Search
Start Over
Conflict-Free Accesses to Strided Vectors on a Banked Cache.
- Source :
- IEEE Transactions on Computers; Jul2005, Vol. 54 Issue 7, p913-916, 4p
- Publication Year :
- 2005
-
Abstract
- With the advance of integration technology, it has become feasible to implement a microprocessor, a vector unit, and a multimegabyte bank-interleaved L2 cache on a single die. Parallel access to strided vectors on the L2 cache is a major performance issue on such vector microprocessors. A major difficulty for such a parallel access is that one would like to interleave the cache on a block size basis in order to benefit from spatial locality and to maintain a low tag volume, while strided vector accesses naturally work on a word granularity. In this paper, we address this issue. Considering a parallel vector unit with 2<superscript>n</superscript> independent lanes, a 2<superscript>n</superscript> bank interleaved cache, and a cache line size of 2<superscript>k</superscript> words, we show that any slice of 2<superscript>n+k</superscript> consecutive elements of any strided vector with stride 2<superscript>r</superscript> R with R odd and r ≤ k can be accessed in the L2 cache and routed back to the lanes in 2<superscript>k</superscript> subslices of 2<superscript>n</superscript> elements. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 00189340
- Volume :
- 54
- Issue :
- 7
- Database :
- Complementary Index
- Journal :
- IEEE Transactions on Computers
- Publication Type :
- Academic Journal
- Accession number :
- 17344461
- Full Text :
- https://doi.org/10.1109/TC.2005.110