Improved Performance Analysis and Design of Dual Metal Gate FinFET for Low Power Digital Applications.

MLA

Padmaja, P., et al. “Improved Performance Analysis and Design of Dual Metal Gate FinFET for Low Power Digital Applications.” International Journal of Engineering Transactions C: Aspects, vol. 37, no. 6, June 2024, pp. 1059–66. EBSCOhost, https://doi.org/10.5829/ije.2024.37.06c.02.

APA

Padmaja, P., Chary, D. V., Erigela, R., Sirisha, G., ChayaDevi, S. K., Pedapudi, M. C., Balaji, B., Cheerala, S., Agarwal, V., & Gowthami, Y. (2024). Improved Performance Analysis and Design of Dual Metal Gate FinFET for Low Power Digital Applications. International Journal of Engineering Transactions C: Aspects, 37(6), 1059–1066. https://doi.org/10.5829/ije.2024.37.06c.02

Chicago

Padmaja, P., D. Vemana Chary, R. Erigela, G. Sirisha, S. K. ChayaDevi, M. C. Pedapudi, B. Balaji, S. Cheerala, V. Agarwal, and Y. Gowthami. 2024. “Improved Performance Analysis and Design of Dual Metal Gate FinFET for Low Power Digital Applications.” International Journal of Engineering Transactions C: Aspects 37 (6): 1059–66. doi:10.5829/ije.2024.37.06c.02.