DBU-PG: energy-efficient noc design using dual-buffering power gating.

With the continuous reduction in transistor size, the power consumption issue associated with the adoption of Network-on-Chips (NoCs) in multicore systems has become increasingly prominent and severe, particularly in terms of static power consumption. Currently, the techniques employed to address the issue of static power consumption in NoCs can be broadly categorized into two forms: power gating and simplified router architecture. However, these designs face critical bottlenecks in maintaining network performance stability and flexibility. In this paper, we propose a power gating approach utilizing double buffering to conserve power. Firstly, we introduce the DBU-PG router architecture, which effectively reduces network power consumption by sharing an input buffer between every two input ports when the network load is low. Secondly, through improved arbitration and flow control mechanisms, packets can be efficiently transmitted between shared buffers. Finally, we propose an improved router architecture, DBU-PG2, which enables packets in different virtual channels of the same buffer to be executed concurrently. Based on evaluation in real application, our DBU-PG and DBU-PG2 routers achieved reductions of 69% and 66%, respectively, in static power consumption compared to the baseline. Additionally, DBU-PG2 reduced packet latency by 7.5% while incurring only a 2.3% increase in area overhead. [ABSTRACT FROM AUTHOR]