High PSR external capacitor‐less LDO with adaptive supply‐ripple cancellation technique.

This work presents an external capacitor‐less low‐dropout regulator (CL‐LDO) with high power supply rejection (PSR) over a wide frequency and load current (IL) range. The high PSR is implemented with an adaptive supply‐ripple cancellation (ASRC) technique. The proposed ASRC circuit consists of a buffer with diode‐connected structure and an adjusting unit. The novel buffer introduces the supply ripple through the diode‐connected transistor to the gate of the pass transistor, enhancing the PSR in the range of 1 MHz. Additionally, the adjusting unit trims the current of the buffer continuously according to the magnitude of IL to optimize the PSR adaptively. Designed in a 55 nm CMOS process with an input voltage of 1.4 V, the proposed LDO achieves −69 dB and −55 dB PSR at 100 KHz and 1 MHz for 50 mA of IL, respectively. Moreover, the maximum current efficiency of the LDO is 99.8% at a full IL of 50 mA. [ABSTRACT FROM AUTHOR]