경량 마이크로컨트롤러를 위한 파편화 제거 기반 온칩 스크래치패드 메모리 효율적 할당.

Cache memory is controlled by hardware, resulting in significant hardware overhead and power consumption. This situation necessitated the use of scratchpad memory as an alternative. Specifically, for utilizing scratchpad memory in multi-core systems, a Local Memory Storage (LMStr) structure has been proposed. However, the LMStr structure must address fragmentation issues caused by the use of variable-sized data blocks. In this paper, we propose a new structure called 'Paging LMStr' that applies paging to solve this problem. We implement a system capable of simulating it in gem5 and evaluate its performance through a comprehensive testbench. The results demonstrate that the proposed structure improves the hit rate by 3.6% and reduces system ticks by approximately 10.68%, leading to a significant overall performance improvement compared to the existing structure. This indicates that Paging LMStr can effectively enhance memory management efficiency in multi-core systems, providing a viable solution to the challenges posed by traditional cache memory systems. [ABSTRACT FROM AUTHOR]