Performance Testing of the Triple Modular Redundancy Mitigation Circuit Test Environment Implementation in Field Programmable Gate Array Structures.

MLA

Kubica, Marcin, and Robert Czerwinski. “Performance Testing of the Triple Modular Redundancy Mitigation Circuit Test Environment Implementation in Field Programmable Gate Array Structures.” Applied Sciences (2076-3417), vol. 14, no. 19, Oct. 2024, p. 8604. EBSCOhost, https://doi.org/10.3390/app14198604.

APA

Kubica, M., & Czerwinski, R. (2024). Performance Testing of the Triple Modular Redundancy Mitigation Circuit Test Environment Implementation in Field Programmable Gate Array Structures. Applied Sciences (2076-3417), 14(19), 8604. https://doi.org/10.3390/app14198604

Chicago

Kubica, Marcin, and Robert Czerwinski. 2024. “Performance Testing of the Triple Modular Redundancy Mitigation Circuit Test Environment Implementation in Field Programmable Gate Array Structures.” Applied Sciences (2076-3417) 14 (19): 8604. doi:10.3390/app14198604.