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SoC-Based Implementation of 1-D Convolutional Neural Network for 3-Channel ECG Arrhythmia Classification via HLS4ML.

Authors :
Ahmad, Feroz
Zafar, Saima
Source :
IEEE Embedded Systems Letters; Dec2024, Vol. 16 Issue 4, p429-432, 4p
Publication Year :
2024

Abstract

Real-time monitoring of 1-D biopotentials, such as electrocardiograms (ECG), necessitates effective feature extraction and classification, a strength of deep learning (DL) algorithms. Designing 1-D convolutional neural network (1-D CNN) accelerators for biopotential classification via open-source codesign workflows, particularly high-level synthesis for machine learning (HLS4ML), offers advantages over GPU-based or cloud-based solutions, including high performance, low latency, low power consumption, swift time-to-market, and cost-effectiveness. We present an implementation of a quantized-pruned (QP) 1-D CNN model on the PYNQ Z2 SoC using HLS4ML by seamlessly deploying its soft IP core generated via Vivado Accelerator backend, showcasing the efficacy of quantization-aware training (QAT) in reducing power consumption to 1.655 W from 1.823 W. Our approach demonstrates improved area consumption, resource utilization, and inferences per second compared to the baseline (B) 1-D CNN model, with a controlled 4% or less reduction in weighted Accuracy, Precision, Recall, and F1-score, revealing the nuanced tradeoffs between performance metrics and system efficiency for real-time 3-channel ECG Arrhythmia classification. [ABSTRACT FROM AUTHOR]

Details

Language :
English
ISSN :
19430663
Volume :
16
Issue :
4
Database :
Complementary Index
Journal :
IEEE Embedded Systems Letters
Publication Type :
Academic Journal
Accession number :
181484114
Full Text :
https://doi.org/10.1109/LES.2024.3354081