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A Pipelined Hardware Implementation of In-loop Deblocking Filter in H.264/AVC .
- Source :
- IEEE Transactions on Consumer Electronics; May2006, Vol. 52 Issue 2, p536-541, 6p, 7 Diagrams, 2 Charts, 1 Graph
- Publication Year :
- 2006
-
Abstract
- In this paper we present a pipelined hardware implementation of In-loop Deblocking Filter in H.264/AVC. A pipelined datapath has been adopted to boost the speed of the deblocking filter process. The processing order of the filter is rearranged to facilitate the deblocking of the pixels in a pipelined fashion. A suitable buffer mechanism has also been proposed that reduces the size of the on-chip SRAM and redundant external memory accesses. The hardware implementation, under TSMC 0.13 µm standard cell library, consumes only 7.5 K gates at a clock frequency of 200MHz. Our architecture supports real-time deblocking of high resolution (2048×1024) video applications at 30 fps over three channels. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 00983063
- Volume :
- 52
- Issue :
- 2
- Database :
- Complementary Index
- Journal :
- IEEE Transactions on Consumer Electronics
- Publication Type :
- Academic Journal
- Accession number :
- 21731008
- Full Text :
- https://doi.org/10.1109/TCE.2006.1649676