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A Defect Tolerance Scheme for Nanotechnology Circuits.
- Source :
- IEEE Transactions on Circuits & Systems. Part I: Regular Papers; Nov2007, Vol. 54 Issue 11, p2402-2409, 8p, 2 Black and White Photographs, 16 Graphs
- Publication Year :
- 2007
-
Abstract
- Lithography-based integrated circuit fabrication is rapidly approaching its limit in terms of feature size. The current alternative is nanotechnology-based fabrication, which relies on self-assembly of nanotubes or nanowires. Such a process is subject to a high defect rate, which can be tolerated using carefully crafted defect tolerance techniques. This paper presents an algorithm for reconfiguration-based defect tolerance in nanotechnology switches. The algorithm offers an average switch density improvement of 50% to 100% to most recently published techniques. The algorithm is also consistent in improving the yield through minimizing false rejects as the results show over a large sample. The improvement percentage varies depending on the manufactured switch size and the desired defect-free size with the improvement in efficiency directly proportional to the size of the switch. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 15498328
- Volume :
- 54
- Issue :
- 11
- Database :
- Complementary Index
- Journal :
- IEEE Transactions on Circuits & Systems. Part I: Regular Papers
- Publication Type :
- Periodical
- Accession number :
- 27710310
- Full Text :
- https://doi.org/10.1109/TCSI.2007.907875