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Systematic-Error Signals in the AC Josephson Voltage Standard: Measurement and Reduction.
- Source :
- IEEE Transactions on Instrumentation & Measurement; Jun2008, Vol. 57 Issue 6, p1215-1220, 6p, 1 Chart, 3 Graphs
- Publication Year :
- 2008
-
Abstract
- We investigate the dominant frequency-dependent systematic-error. signals (SESs) in the ac Josephson voltage standard. We describe our error measurement technique and a num- ber of methods to reduce the errors. Most importantly, we found that a small change in on-chip wiring significantly reduces the SES, improves SES measurement stability, and enables a suitable bias correction method. We show that direct analog-to-digital converter measurements of the SES of two on-chip Josephson arrays are in very good agreement with errors inferred from ac-dc transfer standard measurements. Finally, we demonstrate that the reduction of the SES using these techniques greatly improves the agreement between the ac-dc differences of the two arrays as well as the absolute ac voltage accuracy. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 00189456
- Volume :
- 57
- Issue :
- 6
- Database :
- Complementary Index
- Journal :
- IEEE Transactions on Instrumentation & Measurement
- Publication Type :
- Academic Journal
- Accession number :
- 32046883
- Full Text :
- https://doi.org/10.1109/TIM.2007.915100