Back to Search
Start Over
Co-optimization of Performance and Power in a Superscalar Processor Design.
- Source :
- Emerging Directions in Embedded & Ubiquitous Computing; 2006, p868-878, 11p
- Publication Year :
- 2006
-
Abstract
- As process technology scales down, power wall starts to hinder improvements in processor performance. Performance optimization has to proceed under a power constraint. The co-optimization requires exploration into a huge design space containing both performance and power factors, whose size is over costly for extensive traditional simulations. This paper describes a unified model covering both performance and power. The model consists of workload parameters, architectural parameters plus corresponding power parameters with a good degree of accuracy compared with physical processors and simulators. We apply the model to the problem of co-optimizing the power and performance. Concrete insights into the tradeoffs of designs for performance and power are obtained in the process of co-optimization. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISBNs :
- 9783540368502
- Database :
- Complementary Index
- Journal :
- Emerging Directions in Embedded & Ubiquitous Computing
- Publication Type :
- Book
- Accession number :
- 32717489
- Full Text :
- https://doi.org/10.1007/11807964_87