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Low-Power Test Data Application in EDT Environment Through Decompressor Freeze.

Authors :
Czysz, Dariusz
Mrugalski, Grzegorz
Rajski, Janusz
Tyszer, Jerzy
Source :
IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems; Jul2008, Vol. 27 Issue 7, p1278-1290, 13p
Publication Year :
2008

Abstract

This paper presents a new low-power test scheme integrated with the embedded deterministic test environment. The key contribution of this paper is a flexible test cube encoding scheme, which, in conjunction with a continuous flow decompressor, allows one to significantly reduce toggling rates when test patterns are fed into scan chains. The proposed solution requires neither additional design for testability logic nor modifications to the circuit under test. Experimental results obtained for industrial designs indicate that using this nonintrusive technique reduces switching activity to such extent that the resultant scan-in power consumption is similar to that of the functional mode, thus alleviating problems that are related to average and peak power dissipation, overheating, and risk of reliability degradation. Our approach seamlessly integrates with test logic synthesis flow, and it does not compromise compression ratios. Moreover, it fits well into various design paradigms, including modular design flow where modules come with individual decompressors and compactors. [ABSTRACT FROM AUTHOR]

Details

Language :
English
ISSN :
02780070
Volume :
27
Issue :
7
Database :
Complementary Index
Journal :
IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems
Publication Type :
Academic Journal
Accession number :
33024912
Full Text :
https://doi.org/10.1109/TCAD.2008.923111