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Reliability Issues in Deep Deep Submicron Technologies: Time-Dependent Variability and its Impact on Embedded System Design.

Authors :
De Micheli, Giovanni
Mir, Salvador
Reis, Ricardo
Papanikolaou, Antonis
Wang, Hua
Miranda, Miguel
Catthoor, Francky
Dehaene, Wim
Source :
VLSI-SoC: Research Trends in VLSI & Systems on Chip; 2008, p119-141, 23p
Publication Year :
2008

Abstract

Technology scaling has traditionally offered advantages to embedded systems in terms of reduced energy consumption and die cost as well as increased performance, without requiring significant additional design effort. Scaling past the 45 nm technology node, however, brings a number of problems whose impact on system level design has not been evaluated yet. Random intra-die process variability, reliability degradation mechanisms and their combined impact on the system level parametric quality metrics are prominent issues that will need to be tackled in the next few years. Dealing with these new challenges will require a paradigm shift in the system level design phase. [ABSTRACT FROM AUTHOR]

Details

Language :
English
ISBNs :
9780387749082
Database :
Complementary Index
Journal :
VLSI-SoC: Research Trends in VLSI & Systems on Chip
Publication Type :
Book
Accession number :
33878853
Full Text :
https://doi.org/10.1007/978-0-387-74909-9_8