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A Speed-Optimized Systolic Array Processor Architecture for Spatio-Temporal 2-D hR Broadband Beam Filters.
- Source :
- IEEE Transactions on Circuits & Systems. Part I: Regular Papers; Aug2008, Vol. 55 Issue 7, p1953-1966, 14p, 3 Black and White Photographs, 8 Diagrams, 2 Charts, 3 Graphs
- Publication Year :
- 2008
-
Abstract
- For high-speed plane-wave filtering applications, real-time 2-D spatio-temporal linear-array broadband beam filters are required, operating at temporal frame rates in excess of hundreds of megahertz. The corresponding application specific VLSI circuits must have low critical-path latencies. A novel high-speed systolic array architecture for a first-order 2-D broadband frequency-planar spatio-temporal beam filter is proposed for this purpose and employs a field-programmable gate array (FPGA) circuit where the critical path latency is minimized by timing optimization of inter- and intra-parallel processor pipelines, together with 3-D look-ahead techniques. The method facilitates single-chip VLSI circuit implementations operating at real-time frame rates of several hundred megahertz. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 15498328
- Volume :
- 55
- Issue :
- 7
- Database :
- Complementary Index
- Journal :
- IEEE Transactions on Circuits & Systems. Part I: Regular Papers
- Publication Type :
- Periodical
- Accession number :
- 34217255
- Full Text :
- https://doi.org/10.1109/TCSI.2008.918214