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Low-jitter multi-phase digital DLL with closest edge selection scheme for DDR memory interface.
- Source :
- Electronics Letters (Institution of Engineering & Technology); 9/11/2008, Vol. 44 Issue 19, p1121-1123, 3p, 1 Black and White Photograph, 3 Diagrams, 1 Chart, 1 Graph
- Publication Year :
- 2008
-
Abstract
- A multi-phase digital delay-locked loop (DLL) capable of a low-jitter feature for DDR memory interface is reported. The DLL repeatedly selects the output clock edge which is closest to the reference clock edge to reduce the total jitter. A test chip was fabricated in a 0.18 µm CMOS process to verify its functionality. The measured RMS and peak-to-peak jitter of the DLL are 6.2 and 20.4 ps, respectively. The power consumption of the DLL is 12 mW from a 1.8 V supply voltage. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 00135194
- Volume :
- 44
- Issue :
- 19
- Database :
- Complementary Index
- Journal :
- Electronics Letters (Institution of Engineering & Technology)
- Publication Type :
- Academic Journal
- Accession number :
- 34225047
- Full Text :
- https://doi.org/10.1049/el:20081833