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Dominant Layer for Stress-Induced Positive Charges in Hf-Based Gate Stacks.

Authors :
Zhang, Jian F.
Mo Huai Chang
Zhigang Ji
Lin Lin
Ferain, Isabelle
Groeseneken, Guido
Pantisano, Luigi
De Gendt, Stefan
Heyns, Marc M.
Source :
IEEE Electron Device Letters; Dec2008, Vol. 29 Issue 12, p1360-1363, 4p, 4 Graphs
Publication Year :
2008

Abstract

Positive charges in Hf-based gate stacks play an important role in the negative bias temperature instability of pMOSFETs, and their suppression is a pressing issue. The loca- tion of positive charges is not clear, and central to this letter is determining which layer of the stack dominates positive charging. The results clearly show that positive charges are dominated by the interfacial layer (IL) and that they do not pile up at the HfSiONIIL interface. The results support the assumption that positive charges are located close to the IL/substrate interface. Unlike electron trapping that reduces rapidly for thinner Hf dielectric layer, posi. tive charges cannot be reduced by using a thinner HfSiON film. Index Ternzs-Hf silicates, high-k gate dielectric, instability, negative bias temperature instability (NBTI), positive charges, reliability, spatial distribution. [ABSTRACT FROM AUTHOR]

Details

Language :
English
ISSN :
07413106
Volume :
29
Issue :
12
Database :
Complementary Index
Journal :
IEEE Electron Device Letters
Publication Type :
Academic Journal
Accession number :
35718933
Full Text :
https://doi.org/10.1109/LED.2008.2006288