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Wafer Bumping Process and Inter-Chip Connections for Ultra-High Data Transfer Rates in Multi-Chip Modules With Superconductor Integrated Circuits.
- Source :
- IEEE Transactions on Applied Superconductivity; Jun2009 Part 1 of 3, Vol. 19 Issue 3, p598-602, 5p, 2 Charts, 3 Graphs
- Publication Year :
- 2009
-
Abstract
- Josephson junction logic cells and superconductor microstrip lines are able to process and transfer digital data with rates up to several hundred GHz as has been demonstrated in single-chip experiments. However, the existing chip-level bumping technique in InSn solder and resulting inter-chip connections do not allow expanding these rates to multi-chip circuits. We developed a wafer-level bumping technology using lithographically-defined bumps deposited either by e-beam evaporation or electroplating, and proposed and implemented a novel design of high-frequency chip interconnects. Chip-to-chip single-flux-quantum pulse transmission rates reaching 110 GHz have been achieved. The observed rates were limited not by the interconnects but by the speed of on-chip test circuitry fabricated in the framework of 4.5 kA/cm<superscript>2</superscript> HYPRES process for superconductor integrated circuits. Experimental results on adhesive-bonded and reflow-bonded multi-chip modules (MCMs) with Au and InSn bumps are presented, and effective parameters of the new interconnect design and MCM technology are discussed. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 10518223
- Volume :
- 19
- Issue :
- 3
- Database :
- Complementary Index
- Journal :
- IEEE Transactions on Applied Superconductivity
- Publication Type :
- Academic Journal
- Accession number :
- 43868771
- Full Text :
- https://doi.org/10.1109/TASC.2009.2017858