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A High-Voltage LDMOS Compatible With High-Voltage Integrated Circuits on p-Type SOl Layer.
- Source :
- IEEE Electron Device Letters; Oct2009, Vol. 30 Issue 10, p1093-1095, 3p
- Publication Year :
- 2009
-
Abstract
- Breakdown mechanism for a high-voltage n-channel LDMOS compatible with a high-voltage integrated circuit (HVIC) on a p-type silicon-on-insulator (SOI) layer is investigated theoretically and experimentally. The device is characterized by buried n-islands on a buried oxide layer (BOX). For the proposed structure, ionized donors in n-islands enhance the bottom-interface electric field of the SOI layer from 10 V/μm in the conventional devices on p-SOI layer to 27 V/μm, resulting in enhancement of the BOX electric field E<subscript>I</subscript> from 30 to 82 V/μm. Moreover, holes located between the depleted n-islands help to increase E<subscript>I</subscript> as well. Both improve the blocking capability of the device. A 660-V SOI LDMOS is obtained, in which the implanted n-type drift region, along with the n-islands on a p-type SOI layer, realizes the self-isolation in HVIC. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 07413106
- Volume :
- 30
- Issue :
- 10
- Database :
- Complementary Index
- Journal :
- IEEE Electron Device Letters
- Publication Type :
- Academic Journal
- Accession number :
- 44717098
- Full Text :
- https://doi.org/10.1109/LED.2009.2028249