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Ten-bit 100 MS/s 24.2 mW 0.8 mm2 0.18 µm CMOS pipeline ADC based on maximal circuit sharing schemes.
- Source :
- Electronics Letters (Institution of Engineering & Technology); 12/3/2009, Vol. 45 Issue 25, p1296-1297, 2p, 6 Diagrams, 1 Chart, 1 Graph
- Publication Year :
- 2009
-
Abstract
- A ten-bit (10b) 100 MS/s 0.18 µm CMOS three-step pipeline ADC with various circuit sharing techniques is described. Two MDACs share a single two-stage low-power switched amplifier without MOS series switches and memory effects as observed in conventional shared op-amps. All three flash ADCs use only one resistor ladder rather than three for reference voltages while the second and third flash ADCs share pre-amps for area and power reduction. The prototype ADC with an active die area of 0.80 mm2 shows a maximum SNDR and SFDR of 54.2 and 68.8 dB, respectively, and consumes 24.2 mW at 1.8 V and 100 MS/s. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 00135194
- Volume :
- 45
- Issue :
- 25
- Database :
- Complementary Index
- Journal :
- Electronics Letters (Institution of Engineering & Technology)
- Publication Type :
- Academic Journal
- Accession number :
- 45574937
- Full Text :
- https://doi.org/10.1049/el.2009.2199