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A 1 MHz Bandwidth, 6 GHz 0.18 μm CMOS Type-I ΔΣ Fractional-N Synthesizer for WiMAX Applications.
- Source :
- IEEE Journal of Solid-State Circuits; Dec2009, Vol. 44 Issue 12, p3244-3252, 9p
- Publication Year :
- 2009
-
Abstract
- A 6 GHz Type-I fractional-N PLL with noise-cancelling DAC and discrete-time sample and hold loop-filter is presented. The 1 MHz bandwidth PLL utilizes an inherently linear PFD and noise-cancelling charge-pump DAC circuit to reduce quantization noise by more than 25 dB. The worst case near-integer in-band spur is measured at -61 dBc and the integrated RMS phase error is -42 dBc. The measured in-band phase noise at 300 kHz offset from the 6.12 GHz carrier is -102 dBc/Hz and out-of-band phase noise at 3 MHz offset is -130 dBc/Hz. The PLL loop settling time for an accuracy of 0.01 ppm and a frequency step of 60 MHz is less than 11 μs. The synthesizer is fabricated in a 0.18 μm CMOS technology with 6 metal layers and consumes 26 mA from a 1.8 V power supply. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 00189200
- Volume :
- 44
- Issue :
- 12
- Database :
- Complementary Index
- Journal :
- IEEE Journal of Solid-State Circuits
- Publication Type :
- Academic Journal
- Accession number :
- 47843546
- Full Text :
- https://doi.org/10.1109/JSSC.2009.2032713