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Dual-mode VCO gain topology for reducing in-band noise and reference spur of PLL in 65 nm CMOS.
- Source :
- Electronics Letters (Institution of Engineering & Technology); 3/4/2010, Vol. 46 Issue 5, p335-337, 3p, 1 Color Photograph, 3 Diagrams, 1 Graph
- Publication Year :
- 2010
-
Abstract
- A new topology in PLL architecture dual-mode KVCO (DMK) to reduce in-band noise and reference spurs is presented. The DMK PLL also adopts the technique to shrink the spurs by modulating the control voltage. The prototype DMK PLL is implemented in a 65 nm CMOS and shows about 3 ps RMS jitter, phase noise of -107 and -109 dBc/Hz at 100 kHz, 1 MHz offset frequency and reference spur of 68.5 dBc. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 00135194
- Volume :
- 46
- Issue :
- 5
- Database :
- Complementary Index
- Journal :
- Electronics Letters (Institution of Engineering & Technology)
- Publication Type :
- Academic Journal
- Accession number :
- 48386332
- Full Text :
- https://doi.org/10.1049/el.2010.3553