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Substrate-triggered GGNMOS in 65 nm CMOS process for ESD application.
- Source :
- Electronics Letters (Institution of Engineering & Technology); 4/1/2010, Vol. 46 Issue 7, p518-520, 3p, 1 Diagram, 4 Graphs
- Publication Year :
- 2010
-
Abstract
- A novel substrate-triggered grounded-gate NMOS (GGNMOS) is verified in 65 nm CMOS silicide process. The trigger element is a PMOS controlled by the VDD bus line and no other detection circuit is needed. Compared to traditional GGNMOS, with a 50 µm trigger PMOS, the trigger voltage of the single finger structure can be reduced from 7.15 to 4.97 V and it also has lower overshoot voltage. Also the ultrathin gate oxide can be effectively protected, which is very important in nanometre circuits. For the multi-finger structure, with a 30 µm trigger PMOS the proposed structure showed a 15.9% reduction in trigger voltage and a 13.5% increment as to failure current compared to traditional GGNMOS. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 00135194
- Volume :
- 46
- Issue :
- 7
- Database :
- Complementary Index
- Journal :
- Electronics Letters (Institution of Engineering & Technology)
- Publication Type :
- Academic Journal
- Accession number :
- 48911946
- Full Text :
- https://doi.org/10.1049/el.2010.0205