3-D System Integration of Processor and Multi-Stacked SRAMs Using Inductive-Coupling Link.

MLA

Saen, Makoto, et al. “3-D System Integration of Processor and Multi-Stacked SRAMs Using Inductive-Coupling Link.” IEEE Journal of Solid-State Circuits, vol. 45, no. 4, Apr. 2010, pp. 856–62. EBSCOhost, https://doi.org/10.1109/JSSC.2010.2040310.

APA

Saen, M., Osada, K., Okuma, Y., Niitsu, K., Shimazaki, Y., Sugimori, Y., Kohama, Y., Kasuga, K., Nonomura, I., Irie, N., Hattori, T., Hasegawa, A., & Kuroda, T. (2010). 3-D System Integration of Processor and Multi-Stacked SRAMs Using Inductive-Coupling Link. IEEE Journal of Solid-State Circuits, 45(4), 856–862. https://doi.org/10.1109/JSSC.2010.2040310

Chicago

Saen, Makoto, Kenichi Osada, Yasuyuki Okuma, Kiichi Niitsu, Yasuhisa Shimazaki, Yasufumi Sugimori, Yoshinori Kohama, et al. 2010. “3-D System Integration of Processor and Multi-Stacked SRAMs Using Inductive-Coupling Link.” IEEE Journal of Solid-State Circuits 45 (4): 856–62. doi:10.1109/JSSC.2010.2040310.